1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device having a multi-bit control function, and more specifically, to a technology for selecting a plurality of cells simultaneously and performing data read/write operations using average characteristics of the selected plurality of cells, thereby improving chip operation speed.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated.
The technical contents on the above FRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FRAM are not described herein.
FIG. 1 is a diagram showing a structure of a conventional nonvolatile ferroelectric memory cell.
The conventional nonvolatile ferroelectric memory cell comprises transistors T1 and T2, and ferroelectric capacitors FC1 and FC2. This configuration is called as a ‘2T2C’ (2-Transistor, 2-Capacitor) structure.
The transistor T1, connected between a bitline /BL and a first electrode of the ferroelectric capacitor FC1, has a gate connected to a wordline WL. A second electrode of the ferroelectric capacitor FC1 is connected to a plateline PL. The transistor T2, connected between a bitline BL and a first electrode of the ferroelectric capacitor FC2, has a gate connected to the wordline WL. A second electrode of the ferroelectric capacitor FC2 is connected to the plateline PL.
Here, a pair of bitlines BL and /BL are connected in common to a sense amplifier S/A1. The ferroelectric capacitors FC1 and FC2 store opposite data. One of data is stored in two memory device.
FIG. 2 is a characteristic curve showing a hysteresis loop of a conventional nonvolatile ferroelectric memory cell.
Referring to FIG. 2, in a normal cell, the charge of data “1” is D and the charge of data “0” is A. However, in an abnormal cell, the charge of data “1” is C and the charge of data “0” is B. In the abnormal cell, the data margin of data “1” and “0” represents a minimum value.
When the conventional nonvolatile ferroelectric memory cell having a 2T2C structure has both normal data and abnormal data, a characteristic of a cell is determined by that of abnormal data. As a result, when a cell has a characteristic of abnormal data, it is difficult to distinguish data “1” from data “0” accurately, thereby causing a data failure.
Due to miniaturization of design rule of a semiconductor memory, the cell size becomes smaller. However, as the cell size becomes smaller, it is difficult to maintain the characteristic of a cell. In addition, if the semiconductor memory has a large distribution due to different characteristics of the cell, the minimum sensing margin of data is reduced. As a result, it is impossible to drive a chip rapidly.